Publicaciones

Libros:

• “Timing Performance of Nanometer Digital Circuits Under Process Variations”, Springer, 2018.                          

Revistas indexadas:

• Hector Vazquez-Leal, Mario Alberto Sandoval-Hernandez, J. L. García-Gervacio, Agustin Herrera-May and Uriel Filobello-Nino, PSEM approximations for both branches of Lambert W function with applications», Discrete Dynamics in Nature and Society, Hindawi, 2019.
• Alfonso Herrera Moreno, José Luis García-Gervacio, Héctor Villacorta-Minaya and Héctor Vázquez-Leal, “TCAD analysis and modeling for NBTI mechanism in FinFET transistors”, IEICE Electronics Express (ELEX), 2018.
• Gilberto Domínguez-Rodríguez, José Luis García-Gervacio and Héctor Vázquez-Leal, “Exploring a Homotopy approach for the design of nanometer digital circuits tolerant to process variations”, IEICE Electronics Express (ELEX), 2018.
• J. L. García-Gervacio, Alejandro Nocua-Cifuentes and V. Champac, “Screening Small Delay Defects using Inter-Path Correlation to Reduce Reliability Risk”, Microelectronics Reliability, Elsevier, 2015.
• Hector Villacorta, J. L. García-Gervacio, Jaume Segura and V. Champac, “Low VDD and Body Bias conditions for Testing Bridge Defects in Presence of Process Variations”, Microelectronics Journal, Elsevier, 2015.
• Hector Vazquez-Leal, Brahim Benhammouda, Uriel Filobello-Nino, Arturo Sarmiento-Reyes, Victor Manuel Jimenez-Fernandez, José Luis García-Gervacio, Jesus Huerta-Chua,
Luis Javier Morales-Mendoza and Mario Gonzalez-Lee, “Direct application of Padé approximant for solving nonlinear differential equations ”, SpringerPlus, 2014.
• J. L. García-Gervacio and V. Champac, ”Computing the Probability of Detection of Small Delay Defects of Nanometer ICs”, Journal of Electronic Testing – Theory and Applications (JETTA), Springer, Vol. 27, No. 6, pp. 741-752, 2011.

Memorias en extenso:

• José Adrián Ruiz Carmona, Julio César Muñoz Benítez, José L. García-Gervacio, “SCADA system design: a proposal for optimizing a production line”, IEEE International Conference on Electronics, Communications and Computers (CONIELECOMP), 2016.
• Luis Felipe Lagunes-Aranda, José Luis Garcia-Gervacio, Rubén Alvaro-González, Luis Eduardo-Carrión, Andrea Guadalupe Martínez-Lopez and Jaime Martinez-Castillo, “Testbed Module for UHF Passive RFID Tags”, IEEE International Engineering Summit, II Cumbre Internacional de las Ingenierías (IE-Summit), 2016.
• Sharon Irais Jiménez Reyes, Gregorio Zamora Mejía, Felipe Lagunes-Aranda, José Luis Garcia-Gervacio and Jaime Martinez-Castillo, “Study of failures in interconnection wires between basic digital gates”, IEEE International Conference on Computing and Telematics (ICCSAT), 2015.
• J. L. García-Gervacio, V. Champac and Jaime Martínez, “Possibilities of Defect-Size Magnification for Testing Resistive-Opens in Nanometer Technologies”, IEEE Latin American Test Workshop (LATW’14), Brazil, 2014.
• Zamora-Mejía, J. Martínez-Castillo, J. L. García-Gervacio, A. Díaz-Sanchez, et. al., “Design Methodology for Dickson and Differential Rectifiers for UHF RFID Passive Tags”, Cumbre Internacional de las lngenierías, Coatzacoalcos, Ver. México, October 2013.
• Zamora-Mejía, J. Martínez-Castillo, J. L. García-Gervacio, A. Díaz-Sanchez, et. al., “Front-End Design for UHF RFID Passive Tags”, Conference on Design of Circuits and Integrated Systems (DCIS), España, November 2013.
• Zamora-Mejía, J. Martínez-Castillo, J. L. García-Gervacio, A. Díaz-Sanchez, A. L. Herrera-May, “Voltage Regulation System for UHF RFID Tags”, IEEE Symposium on Integrated Circuits and Systems Design, Brazil, September 2013.
• Hector Villacorta, J. L. García-Gervacio, V. Champac , S. Bota, Jaime Martínez and Jaume Segura, “Bridge Defect Detection in Nanometer CMOS Circuits using Low VDD and Body Bias”, IEEE Latin American Test Workshop (LATW’13), Argentina, 2013.
• J. Galarza-Medina, J. L. García-Gervacio, V. Champac and A. Orailoglu, “Small Delay Defects Detection Under Process Variation Using Inter-Path Correlation”, IEEE VLSI Test Symposium (VTS’12), USA, 2012.
• Martínez-Castillo, G. Zamora-Mejía, J. L. García-Gervacio, S. Salas-Rodríguez and P. García-Ramírez, “Voltage Regulator and ASK Demodulator Design for RFID Passive Tags”, Workshop on Analog and Digital Electronic Design (WADED’11), Mexico, October 2011.
• J. L. García-Gervacio and V. Champac, ”Computing the Detection of Small Delay Defects Caused by Resistive Opens of Nanometer ICs”, IEEE European Test Symposium (ETS’10), Czech Republic, 2010.
• J. L. García-Gervacio and V. Champac, ”A methodology to compute the statistical fault coverage of small delays due to opens”, IEEE Midwest Symposium on Circuits and Systems (MWCAS’09), Mexico, August 2009.
• J. L. García-Gervacio and V. Champac, ”Detectability analysis of small delays due to resistive opens considering process variations”, IEEE International On-Line Test Symposium (IOLTS’09), Portugal, June 2009.
• Iparraguirre-Cardenas, J. L. Garcia-Gervacio, and V. H. Champac, “A design methodology for logic paths tolerant to local intra-die variations,” IEEE International Symposium on Circuits and Systems (ISCAS’08), pp. 596–599, USA, May 2008.
• H. Champac, A. Zenteno and José L. García, ”Testing of Resistive Opens in CMOS Latches and Flip-flops”, IEEE European Test Symposium (ETS’05), pp. 34-40, Estonia, 2005.
• J. L. García-Gervacio and V. H. Champac, ”Optimum vectors test for CMOS memory elements in a scan-path chain”, International Conference on Devices, Circuits and Systems (ICDCSVER’03), Boca del Río, Veracruz, México. July 2003.